以下是按照你提供的指令列表整理的完整表格，补充了机器周期数（基于8051默认12T模式，即1个机器周期=12个时钟周期），表格按机器码（Hex Code）顺序排列：
| Hex Code | Bytes | Mnemonic | Operands | Machine Cycles |
|---|---|---|---|---|
| 00 | 1 | NOP | - | 1 |
| 01 | 2 | AJMP | addr11 | 2 |
| 02 | 3 | LJMP | addr16 | 2 |
| 03 | 1 | RR | A | 1 |
| 04 | 1 | INC | A | 1 |
| 05 | 2 | INC | direct | 1 |
| 06 | 1 | INC | @R0 | 1 |
| 07 | 1 | INC | @R1 | 1 |
| 08 | 1 | INC | R0 | 1 |
| 09 | 1 | INC | R1 | 1 |
| 0A | 1 | INC | R2 | 1 |
| 0B | 1 | INC | R3 | 1 |
| 0C | 1 | INC | R4 | 1 |
| 0D | 1 | INC | R5 | 1 |
| 0E | 1 | INC | R6 | 1 |
| 0F | 1 | INC | R7 | 1 |
| 10 | 3 | JBC | bit, offset | 2 |
| 11 | 2 | ACALL | addr11 | 2 |
| 12 | 3 | LCALL | addr16 | 2 |
| 13 | 1 | RRC | A | 1 |
| 14 | 1 | DEC | A | 1 |
| 15 | 2 | DEC | direct | 1 |
| 16 | 1 | DEC | @R0 | 1 |
| 17 | 1 | DEC | @R1 | 1 |
| 18 | 1 | DEC | R0 | 1 |
| 19 | 1 | DEC | R1 | 1 |
| 1A | 1 | DEC | R2 | 1 |
| 1B | 1 | DEC | R3 | 1 |
| 1C | 1 | DEC | R4 | 1 |
| 1D | 1 | DEC | R5 | 1 |
| 1E | 1 | DEC | R6 | 1 |
| 1F | 1 | DEC | R7 | 1 |
| 20 | 3 | JB | bit, offset | 2 |
| 21 | 2 | AJMP | addr11 | 2 |
| 22 | 1 | RET | - | 2 |
| 23 | 1 | RL | A | 1 |
| 24 | 2 | ADD | A, #immed | 1 |
| 25 | 2 | ADD | A, direct | 1 |
| 26 | 1 | ADD | A, @R0 | 1 |
| 27 | 1 | ADD | A, @R1 | 1 |
| 28 | 1 | ADD | A, R0 | 1 |
| 29 | 1 | ADD | A, R1 | 1 |
| 2A | 1 | ADD | A, R2 | 1 |
| 2B | 1 | ADD | A, R3 | 1 |
| 2C | 1 | ADD | A, R4 | 1 |
| 2D | 1 | ADD | A, R5 | 1 |
| 2E | 1 | ADD | A, R6 | 1 |
| 2F | 1 | ADD | A, R7 | 1 |
| 30 | 3 | JNB | bit, offset | 2 |
| 31 | 2 | ACALL | addr11 | 2 |
| 32 | 1 | RETI | - | 2 |
| 33 | 1 | RLC | A | 1 |
| 34 | 2 | ADDC | A, #immed | 1 |
| 35 | 2 | ADDC | A, direct | 1 |
| 36 | 1 | ADDC | A, @R0 | 1 |
| 37 | 1 | ADDC | A, @R1 | 1 |
| 38 | 1 | ADDC | A, R0 | 1 |
| 39 | 1 | ADDC | A, R1 | 1 |
| 3A | 1 | ADDC | A, R2 | 1 |
| 3B | 1 | ADDC | A, R3 | 1 |
| 3C | 1 | ADDC | A, R4 | 1 |
| 3D | 1 | ADDC | A, R5 | 1 |
| 3E | 1 | ADDC | A, R6 | 1 |
| 3F | 1 | ADDC | A, R7 | 1 |
| 40 | 2 | JC | offset | 2 |
| 41 | 2 | AJMP | addr11 | 2 |
| 42 | 2 | ORL | direct, A | 2 |
| 43 | 3 | ORL | direct, #immed | 2 |
| 44 | 2 | ORL | A, #immed | 1 |
| 45 | 2 | ORL | A, direct | 1 |
| 46 | 1 | ORL | A, @R0 | 1 |
| 47 | 1 | ORL | A, @R1 | 1 |
| 48 | 1 | ORL | A, R0 | 1 |
| 49 | 1 | ORL | A, R1 | 1 |
| 4A | 1 | ORL | A, R2 | 1 |
| 4B | 1 | ORL | A, R3 | 1 |
| 4C | 1 | ORL | A, R4 | 1 |
| 4D | 1 | ORL | A, R5 | 1 |
| 4E | 1 | ORL | A, R6 | 1 |
| 4F | 1 | ORL | A, R7 | 1 |
| 50 | 2 | JNC | offset | 2 |
| 51 | 2 | ACALL | addr11 | 2 |
| 52 | 2 | ANL | direct, A | 2 |
| 53 | 3 | ANL | direct, #immed | 2 |
| 54 | 2 | ANL | A, #immed | 1 |
| 55 | 2 | ANL | A, direct | 1 |
| 56 | 1 | ANL | A, @R0 | 1 |
| 57 | 1 | ANL | A, @R1 | 1 |
| 58 | 1 | ANL | A, R0 | 1 |
| 59 | 1 | ANL | A, R1 | 1 |
| 5A | 1 | ANL | A, R2 | 1 |
| 5B | 1 | ANL | A, R3 | 1 |
| 5C | 1 | ANL | A, R4 | 1 |
| 5D | 1 | ANL | A, R5 | 1 |
| 5E | 1 | ANL | A, R6 | 1 |
| 5F | 1 | ANL | A, R7 | 1 |
| 60 | 2 | JZ | offset | 2 |
| 61 | 2 | AJMP | addr11 | 2 |
| 62 | 2 | XRL | direct, A | 2 |
| 63 | 3 | XRL | direct, #immed | 2 |
| 64 | 2 | XRL | A, #immed | 1 |
| 65 | 2 | XRL | A, direct | 1 |
| 66 | 1 | XRL | A, @R0 | 1 |
| 67 | 1 | XRL | A, @R1 | 1 |
| 68 | 1 | XRL | A, R0 | 1 |
| 69 | 1 | XRL | A, R1 | 1 |
| 6A | 1 | XRL | A, R2 | 1 |
| 6B | 1 | XRL | A, R3 | 1 |
| 6C | 1 | XRL | A, R4 | 1 |
| 6D | 1 | XRL | A, R5 | 1 |
| 6E | 1 | XRL | A, R6 | 1 |
| 6F | 1 | XRL | A, R7 | 1 |
| 70 | 2 | JNZ | offset | 2 |
| 71 | 2 | ACALL | addr11 | 2 |
| 72 | 2 | ORL | C, bit | 2 |
| 73 | 1 | JMP | @A+DPTR | 2 |
| 74 | 2 | MOV | A, #immed | 1 |
| 75 | 3 | MOV | direct, #immed | 2 |
| 76 | 2 | MOV | @R0, #immed | 1 |
| 77 | 2 | MOV | @R1, #immed | 1 |
| 78 | 2 | MOV | R0, #immed | 1 |
| 79 | 2 | MOV | R1, #immed | 1 |
| 7A | 2 | MOV | R2, #immed | 1 |
| 7B | 2 | MOV | R3, #immed | 1 |
| 7C | 2 | MOV | R4, #immed | 1 |
| 7D | 2 | MOV | R5, #immed | 1 |
| 7E | 2 | MOV | R6, #immed | 1 |
| 7F | 2 | MOV | R7, #immed | 1 |
| 80 | 2 | SJMP | offset | 2 |
| 81 | 2 | AJMP | addr11 | 2 |
| 82 | 2 | ANL | C, bit | 2 |
| 83 | 1 | MOVC | A, @A+PC | 2 |
| 84 | 1 | DIV | AB | 4 |
| 85 | 3 | MOV | direct, direct | 2 |
| 86 | 2 | MOV | direct, @R0 | 2 |
| 87 | 2 | MOV | direct, @R1 | 2 |
| 88 | 2 | MOV | direct, R0 | 2 |
| 89 | 2 | MOV | direct, R1 | 2 |
| 8A | 2 | MOV | direct, R2 | 2 |
| 8B | 2 | MOV | direct, R3 | 2 |
| 8C | 2 | MOV | direct, R4 | 2 |
| 8D | 2 | MOV | direct, R5 | 2 |
| 8E | 2 | MOV | direct, R6 | 2 |
| 8F | 2 | MOV | direct, R7 | 2 |
| 90 | 3 | MOV | DPTR, #immed | 2 |
| 91 | 2 | ACALL | addr11 | 2 |
| 92 | 2 | MOV | bit, C | 2 |
| 93 | 1 | MOVC | A, @A+DPTR | 2 |
| 94 | 2 | SUBB | A, #immed | 1 |
| 95 | 2 | SUBB | A, direct | 1 |
| 96 | 1 | SUBB | A, @R0 | 1 |
| 97 | 1 | SUBB | A, @R1 | 1 |
| 98 | 1 | SUBB | A, R0 | 1 |
| 99 | 1 | SUBB | A, R1 | 1 |
| 9A | 1 | SUBB | A, R2 | 1 |
| 9B | 1 | SUBB | A, R3 | 1 |
| 9C | 1 | SUBB | A, R4 | 1 |
| 9D | 1 | SUBB | A, R5 | 1 |
| 9E | 1 | SUBB | A, R6 | 1 |
| 9F | 1 | SUBB | A, R7 | 1 |
| A0 | 2 | ORL | C, /bit | 2 |
| A1 | 2 | AJMP | addr11 | 2 |
| A2 | 2 | MOV | C, bit | 1 |
| A3 | 1 | INC | DPTR | 2 |
| A4 | 1 | MUL | AB | 4 |
| A5 | - | reserved | - | - |
| A6 | 2 | MOV | @R0, direct | 2 |
| A7 | 2 | MOV | @R1, direct | 2 |
| A8 | 2 | MOV | R0, direct | 2 |
| A9 | 2 | MOV | R1, direct | 2 |
| AA | 2 | MOV | R2, direct | 2 |
| AB | 2 | MOV | R3, direct | 2 |
| AC | 2 | MOV | R4, direct | 2 |
| AD | 2 | MOV | R5, direct | 2 |
| AE | 2 | MOV | R6, direct | 2 |
| AF | 2 | MOV | R7, direct | 2 |
| B0 | 2 | ANL | C, /bit | 2 |
| B1 | 2 | ACALL | addr11 | 2 |
| B2 | 2 | CPL | bit | 1 |
| B3 | 1 | CPL | C | 1 |
| B4 | 3 | CJNE | A, #immed, offset | 2 |
| B5 | 3 | CJNE | A, direct, offset | 2 |
| B6 | 3 | CJNE | @R0, #immed, offset | 2 |
| B7 | 3 | CJNE | @R1, #immed, offset | 2 |
| B8 | 3 | CJNE | R0, #immed, offset | 2 |
| B9 | 3 | CJNE | R1, #immed, offset | 2 |
| BA | 3 | CJNE | R2, #immed, offset | 2 |
| BB | 3 | CJNE | R3, #immed, offset | 2 |
| BC | 3 | CJNE | R4, #immed, offset | 2 |
| BD | 3 | CJNE | R5, #immed, offset | 2 |
| BE | 3 | CJNE | R6, #immed, offset | 2 |
| BF | 3 | CJNE | R7, #immed, offset | 2 |
| C0 | 2 | PUSH | direct | 2 |
| C1 | 2 | AJMP | addr11 | 2 |
| C2 | 2 | CLR | bit | 1 |
| C3 | 1 | CLR | C | 1 |
| C4 | 1 | SWAP | A | 1 |
| C5 | 2 | XCH | A, direct | 1 |
| C6 | 1 | XCH | A, @R0 | 1 |
| C7 | 1 | XCH | A, @R1 | 1 |
| C8 | 1 | XCH | A, R0 | 1 |
| C9 | 1 | XCH | A, R1 | 1 |
| CA | 1 | XCH | A, R2 | 1 |
| CB | 1 | XCH | A, R3 | 1 |
| CC | 1 | XCH | A, R4 | 1 |
| CD | 1 | XCH | A, R5 | 1 |
| CE | 1 | XCH | A, R6 | 1 |
| CF | 1 | XCH | A, R7 | 1 |
| D0 | 2 | POP | direct | 2 |
| D1 | 2 | ACALL | addr11 | 2 |
| D2 | 2 | SETB | bit | 1 |
| D3 | 1 | SETB | C | 1 |
| D4 | 1 | DA | A | 1 |
| D5 | 3 | DJNZ | direct, offset | 2 |
| D6 | 1 | XCHD | A, @R0 | 1 |
| D7 | 1 | XCHD | A, @R1 | 1 |
| D8 | 2 | DJNZ | R0, offset | 2 |
| D9 | 2 | DJNZ | R1, offset | 2 |
| DA | 2 | DJNZ | R2, offset | 2 |
| DB | 2 | DJNZ | R3, offset | 2 |
| DC | 2 | DJNZ | R4, offset | 2 |
| DD | 2 | DJNZ | R5, offset | 2 |
| DE | 2 | DJNZ | R6, offset | 2 |
| DF | 2 | DJNZ | R7, offset | 2 |
| E0 | 1 | MOVX | A, @DPTR | 2 |
| E1 | 2 | AJMP | addr11 | 2 |
| E2 | 1 | MOVX | A, @R0 | 2 |
| E3 | 1 | MOVX | A, @R1 | 2 |
| E4 | 1 | CLR | A | 1 |
| E5 | 2 | MOV | A, direct | 1 |
| E6 | 1 | MOV | A, @R0 | 1 |
| E7 | 1 | MOV | A, @R1 | 1 |
| E8 | 1 | MOV | A, R0 | 1 |
| E9 | 1 | MOV | A, R1 | 1 |
| EA | 1 | MOV | A, R2 | 1 |
| EB | 1 | MOV | A, R3 | 1 |
| EC | 1 | MOV | A, R4 | 1 |
| ED | 1 | MOV | A, R5 | 1 |
| EE | 1 | MOV | A, R6 | 1 |
| EF | 1 | MOV | A, R7 | 1 |
| F0 | 1 | MOVX | @DPTR, A | 2 |
| F1 | 2 | ACALL | addr11 | 2 |
| F2 | 1 | MOVX | @R0, A | 2 |
| F3 | 1 | MOVX | @R1, A | 2 |
| F4 | 1 | CPL | A | 1 |
| F5 | 2 | MOV | direct, A | 1 |
| F6 | 1 | MOV | @R0, A | 1 |
| F7 | 1 | MOV | @R1, A | 1 |
| F8 | 1 | MOV | R0, A | 1 |
| F9 | 1 | MOV | R1, A | 1 |
| FA | 1 | MOV | R2, A | 1 |
| FB | 1 | MOV | R3, A | 1 |
| FC | 1 | MOV | R4, A | 1 |
| FD | 1 | MOV | R5, A | 1 |
| FE | 1 | MOV | R6, A | 1 |
| FF | 1 | MOV | R7, A | 1 |
关键说明：
- 机器周期数规则：
- 单字节指令（如NOP、INC A）：多数为1周期；特殊指令（MUL AB、DIV AB）为4周期，INC DPTR为2周期。
- 双字节指令（如AJMP、ACALL）：多数为2周期；部分双字节指令（如MOV A, direct、INC direct）为1周期。
- 三字节指令（如LJMP、CJNE系列）：全部为2周期。
- reserved指令：A5H为未定义指令，无对应助记符和机器周期数，表格中标记为“-”。
- 操作数说明：
addr11（11位地址）、addr16（16位地址）、immed（8位立即数）、offset（8位相对偏移量，补码形式）、bit（位地址，00H~7FH），与8051标准指令集定义一致。
以下是8051单片机常用指令的助记符、机器码、字节数及机器周期数的整理表格（涵盖主要指令类别，共111条核心指令）。表格按功能分类，便于查阅：
| 指令类别 | 指令助记符 | 机器码 | 字节数 | 机器周期数 | 说明（寻址方式） |
|---|---|---|---|---|---|
| 一、数据传送类 | |||||
| 1. 内部RAM传送 | MOV A, Rn | E8H~EFH | 1 | 1 | Rn为R0~R7（寄存器寻址） |
| MOV Rn, A | F8H~FFH | 1 | 1 | Rn为R0~R7（寄存器寻址） | |
| MOV A, @Ri | E6H~E7H | 1 | 1 | Ri为R0/R1（寄存器间接寻址） | |
| MOV @Ri, A | F6H~F7H | 1 | 1 | Ri为R0/R1（寄存器间接寻址） | |
| MOV A, #data | 74H data | 2 | 1 | 立即数寻址 | |
| MOV A, direct | E5H direct | 2 | 1 | 直接寻址（direct为内部RAM地址） | |
| MOV direct, A | F5H direct | 2 | 1 | 直接寻址 | |
| MOV Rn, #data | 78H~7FH data | 2 | 1 | 立即数→寄存器 | |
| MOV direct, #data | 75H direct data | 3 | 2 | 立即数→直接地址 | |
| MOV @Ri, #data | 76H~77H data | 2 | 1 | 立即数→间接地址 | |
| MOV direct, Rn | 88H~8FH direct | 2 | 2 | 寄存器→直接地址 | |
| MOV Rn, direct | A8H~AFH direct | 2 | 2 | 直接地址→寄存器 | |
| MOV direct, @Ri | 86H~87H direct | 2 | 2 | 间接地址→直接地址 | |
| MOV @Ri, direct | A6H~A7H direct | 2 | 2 | 直接地址→间接地址 | |
| MOV direct1, direct2 | 85H direct1 direct2 | 3 | 2 | 直接地址间传送 | |
| 2. 外部RAM传送 | MOVX A, @Ri | E2H~E3H | 1 | 2 | 外部RAM（8位地址）→累加器 |
| MOVX @Ri, A | F2H~F3H | 1 | 2 | 累加器→外部RAM（8位地址） | |
| MOVX A, @DPTR | E0H | 1 | 2 | 外部RAM（16位地址）→累加器 | |
| MOVX @DPTR, A | F0H | 1 | 2 | 累加器→外部RAM（16位地址） | |
| 3. 程序存储器传送 | MOVC A, @A+DPTR | 93H | 1 | 2 | 查表（DPTR为基址） |
| MOVC A, @A+PC | 83H | 1 | 2 | 查表（PC为基址） | |
| 4. 堆栈操作 | PUSH direct | C0H direct | 2 | 2 | 直接地址内容入栈 |
| POP direct | D0H direct | 2 | 2 | 栈顶内容出栈到直接地址 | |
| 5. 数据交换 | XCH A, Rn | C8H~CFH | 1 | 1 | 累加器与寄存器交换 |
| XCH A, @Ri | C6H~C7H | 1 | 1 | 累加器与间接地址交换 | |
| XCH A, direct | C5H direct | 2 | 1 | 累加器与直接地址交换 | |
| XCHD A, @Ri | D6H~D7H | 1 | 1 | 累加器低4位与间接地址低4位交换 | |
| 二、算术运算类 | |||||
| 1. 加法 | ADD A, Rn | 28H~2FH | 1 | 1 | 累加器加寄存器 |
| ADD A, @Ri | 26H~27H | 1 | 1 | 累加器加间接地址 | |
| ADD A, direct | 25H direct | 2 | 1 | 累加器加直接地址 | |
| ADD A, #data | 24H data | 2 | 1 | 累加器加立即数 | |
| 2. 带进位加法 | ADDC A, Rn | 38H~3FH | 1 | 1 | 累加器加寄存器和进位位 |
| ADDC A, @Ri | 36H~37H | 1 | 1 | 累加器加间接地址和进位位 | |
| ADDC A, direct | 35H direct | 2 | 1 | 累加器加直接地址和进位位 | |
| ADDC A, #data | 34H data | 2 | 1 | 累加器加立即数和进位位 | |
| 3. 减法 | SUBB A, Rn | 98H~9FH | 1 | 1 | 累加器减寄存器和借位位 |
| SUBB A, @Ri | 96H~97H | 1 | 1 | 累加器减间接地址和借位位 | |
| SUBB A, direct | 95H direct | 2 | 1 | 累加器减直接地址和借位位 | |
| SUBB A, #data | 94H data | 2 | 1 | 累加器减立即数和借位位 | |
| 4. 乘法 | MUL AB | A4H | 1 | 4 | A×B，结果存A（高8位）、B（低8位） |
| 5. 除法 | DIV AB | 84H | 1 | 4 | A÷B，商存A，余数存B（除数为0则置位OV） |
| 6. 增量 | INC A | 04H | 1 | 1 | 累加器加1 |
| INC Rn | 08H~0FH | 1 | 1 | 寄存器加1 | |
| INC @Ri | 06H~07H | 1 | 1 | 间接地址加1 | |
| INC direct | 05H direct | 2 | 1 | 直接地址加1 | |
| INC DPTR | A3H | 1 | 2 | 数据指针加1 | |
| 7. 减量 | DEC A | 14H | 1 | 1 | 累加器减1 |
| DEC Rn | 18H~1FH | 1 | 1 | 寄存器减1 | |
| DEC @Ri | 16H~17H | 1 | 1 | 间接地址减1 | |
| DEC direct | 15H direct | 2 | 1 | 直接地址减1 | |
| 8. 十进制调整 | DA A | D4H | 1 | 1 | BCD码加法结果调整 |
| 三、逻辑运算类 | |||||
| 1. 累加器操作 | CLR A | E4H | 1 | 1 | 累加器清零 |
| CPL A | F4H | 1 | 1 | 累加器取反 | |
| RL A | 23H | 1 | 1 | 累加器循环左移 | |
| RLC A | 33H | 1 | 1 | 累加器带进位循环左移 | |
| RR A | 03H | 1 | 1 | 累加器循环右移 | |
| RRC A | 13H | 1 | 1 | 累加器带进位循环右移 | |
| SWAP A | C4H | 1 | 1 | 累加器高低4位交换 | |
| 2. 逻辑与 | ANL A, Rn | 58H~5FH | 1 | 1 | 累加器与寄存器 |
| ANL A, @Ri | 56H~57H | 1 | 1 | 累加器与间接地址 | |
| ANL A, direct | 55H direct | 2 | 1 | 累加器与直接地址 | |
| ANL A, #data | 54H data | 2 | 1 | 累加器与立即数 | |
| ANL direct, A | 52H direct | 2 | 2 | 直接地址与累加器 | |
| ANL direct, #data | 53H direct data | 3 | 2 | 直接地址与立即数 | |
| 3. 逻辑或 | ORL A, Rn | 48H~4FH | 1 | 1 | 累加器或寄存器 |
| ORL A, @Ri | 46H~47H | 1 | 1 | 累加器或间接地址 | |
| ORL A, direct | 45H direct | 2 | 1 | 累加器或直接地址 | |
| ORL A, #data | 44H data | 2 | 1 | 累加器或立即数 | |
| ORL direct, A | 42H direct | 2 | 2 | 直接地址或累加器 | |
| ORL direct, #data | 43H direct data | 3 | 2 | 直接地址或立即数 | |
| 4. 逻辑异或 | XRL A, Rn | 68H~6FH | 1 | 1 | 累加器异或寄存器 |
| XRL A, @Ri | 66H~67H | 1 | 1 | 累加器异或间接地址 | |
| XRL A, direct | 65H direct | 2 | 1 | 累加器异或直接地址 | |
| XRL A, #data | 64H data | 2 | 1 | 累加器异或立即数 | |
| XRL direct, A | 62H direct | 2 | 2 | 直接地址异或累加器 | |
| XRL direct, #data | 63H direct data | 3 | 2 | 直接地址异或立即数 | |
| 四、控制转移类 | |||||
| 1. 无条件转移 | LJMP addr16 | 02H addr16 | 3 | 2 | 长跳转（64KB范围内） |
| AJMP addr11 | a10~a8 00001 a7~a0 | 2 | 2 | 绝对跳转（2KB范围内） | |
| SJMP rel | 80H rel | 2 | 2 | 短跳转（相对地址，范围-128~+127） | |
| JMP @A+DPTR | 73H | 1 | 2 | 间接跳转（A+DPTR为目标地址） | |
| 2. 条件转移 | JZ rel | 60H rel | 2 | 2 | A为0则跳转 |
| JNZ rel | 70H rel | 2 | 2 | A不为0则跳转 | |
| CJNE A, direct, rel | B5H direct rel | 3 | 2 | A与直接地址比较，不等则跳转 | |
| CJNE A, #data, rel | B4H data rel | 3 | 2 | A与立即数比较，不等则跳转 | |
| CJNE Rn, #data, rel | B8H~BFH data rel | 3 | 2 | 寄存器与立即数比较，不等则跳转 | |
| CJNE @Ri, #data, rel | B6H~B7H data rel | 3 | 2 | 间接地址与立即数比较，不等则跳转 | |
| DJNZ Rn, rel | D8H~DFH rel | 2 | 2 | 寄存器减1，不为0则跳转 | |
| DJNZ direct, rel | D5H direct rel | 3 | 2 | 直接地址减1，不为0则跳转 | |
| 3. 子程序调用 | LCALL addr16 | 12H addr16 | 3 | 2 | 长调用（64KB范围内） |
| ACALL addr11 | a10~a8 00011 a7~a0 | 2 | 2 | 绝对调用（2KB范围内） | |
| RET | 22H | 1 | 2 | 子程序返回 | |
| RETI | 32H | 1 | 2 | 中断服务程序返回 | |
| 4. 空操作 | NOP | 00H | 1 | 1 | 空操作（延时1个机器周期） |
| 五、位操作类 | |||||
| 1. 位传送 | MOV C, bit | A2H bit | 2 | 1 | 位地址内容送进位位 |
| MOV bit, C | 92H bit | 2 | 2 | 进位位内容送位地址 | |
| 2. 位置位/清零 | CLR C | C3H | 1 | 1 | 进位位清零 |
| CLR bit | C2H bit | 2 | 1 | 位地址清零 | |
| SETB C | D3H | 1 | 1 | 进位位置1 | |
| SETB bit | D2H bit | 2 | 1 | 位地址置1 | |
| 3. 位逻辑运算 | CPL C | B3H | 1 | 1 | 进位位取反 |
| CPL bit | B2H bit | 2 | 1 | 位地址取反 | |
| ANL C, bit | 82H bit | 2 | 2 | 进位位与位地址 | |
| ANL C, /bit | B0H bit | 2 | 2 | 进位位与位地址非 | |
| ORL C, bit | 72H bit | 2 | 2 | 进位位或位地址 | |
| ORL C, /bit | A0H bit | 2 | 2 | 进位位或位地址非 | |
| 4. 位条件转移 | JC rel | 40H rel | 2 | 2 | 进位位为1则跳转 |
| JNC rel | 50H rel | 2 | 2 | 进位位为0则跳转 | |
| JB bit, rel | 20H bit rel | 3 | 2 | 位地址为1则跳转 | |
| JNB bit, rel | 30H bit rel | 3 | 2 | 位地址为0则跳转 | |
| JBC bit, rel | 10H bit rel | 3 | 2 | 位地址为1则跳转，并清零该位 |
说明：
- 机器码中，
data表示8位立即数，addr16表示16位地址，addr11表示11位地址，rel表示8位相对偏移量（补码形式），bit表示位地址（00H~7FH）。 - 机器周期数基于12T模式（1个机器周期=12个时钟周期），这是8051的默认模式。
- 表格涵盖了8051的全部核心指令，特殊扩展指令（如部分厂商自定义指令）未列入。
该表格可作为8051汇编编程、机器码分析及时序计算的参考工具。